Systems and methods for transforming a central processing unit (cpu) socket into a memory and/or input/output (i/o) expander

ABSTRACT

Systems and methods for transforming a Central Processing Unit (CPU) socket into a memory and/or Input/Output (I/O) expander. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a plurality of CPU sockets, each of the CPU sockets having one or more cores, and each of the one or more cores being associated with a respective one or more electronic circuits, the one or more electronic circuits including at least one of: a memory controller or an input/output (I/O) controller; and a Basic Input/Output System (BIOS) circuit coupled to the plurality of CPU sockets, the BIOS circuit having access to program instructions that, upon execution by the BIOS, cause the IHS to: initialize the plurality of CPU sockets; and report an electronic circuit associated to a first core of a first CPU socket as being instead associated with a second core of a second CPU socket.

FIELD

This disclosure relates generally to computer systems, and morespecifically, to systems and methods for transforming a CentralProcessing Unit (CPU) socket into a memory and/or Input/Output (I/O)expander.

BACKGROUND

As the value and use of information continues to increase, individualsand businesses seek additional ways to process and store information.One option is an Information Handling System (IHS). An IHS generallyprocesses, compiles, stores, and/or communicates information or data forbusiness, personal, or other purposes. Because technology andinformation handling needs and requirements may vary between differentapplications, IHSs may also vary regarding what information is handled,how the information is handled, how much information is processed,stored, or communicated, and how quickly and efficiently the informationmay be processed, stored, or communicated. The variations in IHSs allowfor IHSs to be general or configured for a specific user or specific usesuch as financial transaction processing, airline reservations,enterprise data storage, global communications, etc. In addition, IHSsmay include a variety of hardware and software components that may beconfigured to process, store, and communicate information and mayinclude one or more computer systems, data storage systems, andnetworking systems.

An IHS may be designed with a multi-core processor. A multi-coreprocessor is a single computing component with two or more independentprocessing cores that are able to read and execute program instructionsor software code. These multiple cores can run multiple instructionsconcurrently, thus increasing the overall processing speed for programs.Multiple cores typically are integrated onto a single integrated circuitdie or integrated circuit or onto multiple dies in a single chippackage, generally referred to as the IHS's Central Processing Unit(CPU). In some cases, a single IHS may include two or more multi-coreCPUs.

Each multi-core processor may include one or more “CPU sockets.” EachCPU socket may in turn have, for example, one or more processor cores,one or more memory controllers (which allow for dual in-line memorymodule(s) external to CPU socket), and one or more Peripheral ComponentInterconnect Express (PCIe) Input/Output (I/O) lanes.

The inventors hereof have recognized that certain software products(e.g., virtualization and virtual machine software) is licensed basedupon a number of CPU sockets present in a given IHS, while certain othersoftware products (certain database, Computer-aided design (CAD),Electronic design automation (EDA), etc.) are licensed based on numberof CPU cores present in the given IHS. A good portion of these licensedsoftware benefits from larger amounts of system memory. As a result,majority of customers end up purchasing servers with more CPU socketsjust to get adequate amount of system memory. Lately, the number ofcores in CPU sockets has been doubling every 2-3 years. However, theavailable memory and I/O circuitry has not historically increased at thesame rate as the number of cores. In fact, in most virtualizedapplications, often the most significant performance limiting factor isinsufficient memory; not the available number of cores.

Accordingly, the inventors hereof have identified a demand for largermemories (e.g., 24 DIMMs per socket instead of across two sockets)and/or I/O ports to be used with a smaller number of CPU sockets (e.g.,one or two) within a multi-core processor, in order to reduce softwarelicensing costs in certain applications.

SUMMARY

Embodiments of systems and methods for transforming a Central ProcessingUnit (CPU) socket into a memory and/or Input/Output (I/O) expander aredescribed herein. In an illustrative, non-limiting embodiment, anInformation Handling System (IHS) may include a plurality of CentralProcessing Unit (CPU) sockets, each of the CPU sockets having one ormore cores, and each of the one or more cores being associated with arespective one or more electronic circuits, the one or more electroniccircuits including at least one of: a memory controller or aninput/output (I/O) controller; and a Basic Input/Output System (BIOS)circuit coupled to the plurality of CPU sockets, the BIOS circuit havingaccess to program instructions that, upon execution by the BIOS, causethe IHS to: initialize the plurality of CPU sockets; and report anelectronic circuit associated to a first core of a first CPU socket asbeing instead associated with a second core of a second CPU socket.

In some cases, the plurality of CPU sockets may include a singlemulti-core processor. Each of core in each of the plurality of CPUsockets may be configured to operate as a discrete logical processor.The electronic circuit associated with the first core of the first CPUsocket may be physically disposed closer to the first core than to thesecond core of the second CPU socket. Each of the memory controllers maybe configured to communicate with one or more dual in-line memorymodules (DIMMs). Also, the reporting operation may occur before the IHSboots into an Operating System (OS).

The program instructions, upon execution by the BIOS, may cause the IHSto: create or modify a Local Advanced Programmable Interrupt Controller(LAPIC) table of an Advanced Configuration and Power Interface (ACPI)to: identify at least one of: the second CPU socket or a number ofcore(s) of the second CPU socket; and not identify the first CPU socketas having any cores. Additionally or alternatively, the programinstructions, upon execution by the BIOS, may further cause the IHS tomodify an Advanced Configuration and Power Interface (ACPI) StaticResource Affinity Table (SRAT) to identify the memory controllerassociated with the first core of the first CPU socket as being coupleddirectly to the second core of the second CPU socket. Additionally oralternatively, the program instructions, upon execution by the BIOS, mayfurther cause the IHS to create or modify an Advanced Configuration andPower Interface (ACPI) System Locality Information Table (SLIT) toidentify the memory controller associated with the first core of thefirst CPU socket as including a remote memory coupled to the second coreof the second CPU socket. Additionally or alternatively, the programinstructions, upon execution by the BIOS, may further cause the IHS tocreate or modify Advanced Configuration and Power Interface (ACPI)proximity (PXM) information to report one or more Peripheral ComponentInterconnect Express (PCIe) root ports associated with the first core ofthe first CPU socket as logical PCIe root ports belonging to the secondcore of the second CPU socket. Additionally or alternatively, theprogram instructions, upon execution by the BIOS, may further cause theIHS to, in response to a System Management Mode (SMM) of operation beinginvoked to address a memory or I/O error of the first core of the firstCPU socket during Operating System (OS) runtime, report the error ashaving been originated by the second core of the second CPU socket.

In another illustrative, non-limiting embodiment, a computer-implementedmethod, may include: initializing a plurality of Central Processing Unit(CPU) sockets within a multi-core processor of an Information HandlingSystem (IHS); and prior to the IHS booting an Operating System (OS),reporting an electronic circuit of a first core of a first CPU socket asbelonging to a second core of a second CPU socket. For example, theelectronic circuit may include a memory controller local to the firstcore of the first CPU socket and/or an Input/Output (I/O) extender localto the first core of the first CPU socket.

The method may further comprise creating or modifying a Local AdvancedProgrammable Interrupt Controller (LAPIC) table of an AdvancedConfiguration and Power Interface (ACPI), wherein the LAPIC table isconfigured to identify the second core of the second CPU socket, andwherein the LAPIC table is configured not to identify the first core ofthe first CPU socket.

Additionally or alternatively, the method may further comprise creatingor modifying an Advanced Configuration and Power Interface (ACPI) StaticResource Affinity Table (SRAT) to identify the memory controller asbeing coupled directly to the second core of the second CPU socket.Additionally or alternatively, the method may further comprise creatingor modifying an Advanced Configuration and Power Interface (ACPI) SystemLocality Information Table (SLIT) to identify the memory controller asincluding a remote memory coupled to the second core of the second CPUsocket. Additionally or alternatively, the method may further comprisemodifying Advanced Configuration and Power Interface (ACPI) proximity(PXM) information to report one or more Peripheral ComponentInterconnect Express (PCIe) root ports local to the first core of thefirst CPU socket as logical PCIe root ports local to the second core ofthe second CPU socket. Additionally or alternatively, the method mayfurther comprise, in response to a System Management Mode (SMM) ofoperation being invoked to address a memory or I/O error of the firstcore of the first CPU socket during Operating System (OS) runtime,reporting the error as having been originated by the second core of thesecond CPU socket.

In yet another illustrative, non-limiting embodiment, a non-transitorycomputer-readable medium may have program instructions stored thereonthat, upon execution by an Information Handling System (IHS), cause theIHS to: initialize a plurality of Central Processing Unit (CPU) sockets;create or modify a Local Advanced Programmable Interrupt Controller(LAPIC) table of an Advanced Configuration and Power Interface (ACPI),wherein the LAPIC table is configured to identify a second core of asecond CPU socket, and wherein the LAPIC table is configured not toidentify a first core of a first CPU socket; create or modify an ACPIStatic Resource Affinity Table (SRAT) to identify a memory controllercorresponding to the first core of the first CPU socket as beingassociated with the second core of the second CPU socket; create ormodify an ACPI System Locality Information Table (SLIT) to identify thememory controller as including a remote memory coupled to the secondcore of the second CPU socket; and in response to a System ManagementMode (SMM) of operation being invoked to address a memory or I/O errorof the first core of the first CPU socket during Operating System (OS)runtime, reporting the error as having been originated by the secondcore of the second CPU socket.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention(s) is/are illustrated by way of example and is/arenot limited by the accompanying figures, in which like referencesindicate similar elements. Elements in the figures are illustrated forsimplicity and clarity, and have not necessarily been drawn to scale.

FIG. 1 illustrates an example IHS configured to implement varioussystems and methods described herein according to some embodiments.

FIG. 2 illustrates an example of core configuration parameters beingtransmitted from a basic input output system (BIOS) to a processorcontrol logic according to some embodiments.

FIG. 3 is a flowchart illustrating an example of a method fortransforming a Central Processing Unit (CPU) socket into a memory and/orInput/Output (I/O) expander according to some embodiments.

FIGS. 4 and 5 illustrate an example of a FlexMemBridge configurationaccording to some embodiments.

DETAILED DESCRIPTION

Systems and methods for transforming a Central Processing Unit (CPU)socket into a memory and/or Input/Output (I/O) expander are described.As used herein, the term “CPU socket” refers to a combination of one ormore processor core(s), one or more memory controller(s), and I/Ocircuitry local to or otherwise associated with corresponding processorcore(s). In various implementations, a multi-core processor of anInformation Handling System (IHS) may include a plurality of CPU sockets(e.g., 2, 4, etc.), and each CPU socket may include a number of cores.

In some cases, software licenses may be issued on a per-core basis. Forexample, if an IHS' multi-core processor includes two CPU sockets, eachsocket with its own single core, at least two licenses would ordinarilybe needed in order for the IHS to execute certain licensedvirtualization programs when those programs are licensed on a per-corebasis. In contrast, by implementing systems and methods describedherein, the IHS may be initialized with only one of the two CPU socketsusing its processing core as such.

A first core of a first CPU socket may instead be transformed into amemory and/or I/O expander via firmware, such that a second core of asecond CPU socket effectively has access to two sets of dual in-linememory modules (DIMMs)—that is, the second CPU core of the second CPUsocket has access to a second set of DIMMs that is associated with thesecond core by default, and it also has access to a first set of DIMMslocal to the first core of the first CPU socket as if it were its own.Prior to the IHS' operating system being booted, the first socket may bereported to the system as having “zero cores,” but full memory and/orI/O controllers. Hence, the per-core costs of certain licensed softwaremay be significantly reduced.

In the following detailed description of exemplary embodiments of thedisclosure, specific exemplary embodiments in which the disclosure maybe practiced are described in sufficient detail a person of ordinaryskill in the art to practice the disclosed embodiments. For example,specific details such as specific method orders, structures, elements,and connections have been presented herein. However, it is to beunderstood that the specific details presented need not be utilized topractice embodiments of the present disclosure. It is also to beunderstood that other embodiments may be utilized and that logical,architectural, programmatic, mechanical, electrical and other changesmay be made without departing from general scope of the disclosure. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present disclosure is defined bythe appended claims and equivalents thereof.

References within the specification to “one embodiment,” “anembodiment,” “embodiments”, or “one or more embodiments” are intended toindicate that a particular feature, structure, or characteristicdescribed in connection with the embodiment is included in at least oneembodiment of the present disclosure. The appearance of such phrases invarious places within the specification are not necessarily allreferring to the same embodiment, nor are separate or alternativeembodiments mutually exclusive of other embodiments. Further, variousfeatures are described which may be exhibited by some embodiments andnot by others. Similarly, various requirements are described which maybe requirements for some embodiments but not other embodiments.

It is understood that the use of specific component, device and/orparameter names and/or corresponding acronyms thereof, such as those ofthe executing utility, logic, and/or firmware described herein, are forexample only and not meant to imply any limitations on the describedembodiments. The embodiments may thus be described with differentnomenclature and/or terminology utilized to describe the components,devices, parameters, methods and/or functions herein, withoutlimitation. References to any specific protocol or proprietary name indescribing one or more elements, features or concepts of the embodimentsare provided solely as examples of one implementation, and suchreferences do not limit the extension of the claimed embodiments toembodiments in which different element, feature, protocol, or conceptnames are utilized. Thus, each term utilized herein is to be given itsbroadest interpretation given the context in which that terms isutilized.

For purposes of this disclosure, an IHS, such as IHS 100, may includeany instrumentality or aggregate of instrumentalities operable tocompute, classify, process, transmit, receive, retrieve, originate,switch, store, display, manifest, detect, record, reproduce, handle, orutilize any form of information, intelligence, or data for business,scientific, control, or other purposes. For example, an IHS may be ahandheld device, personal computer, a server, a network storage device,or any other suitable device and may vary in size, shape, performance,functionality, and price. The IHS may include random access memory(RAM), one or more processing resources such as a CPU or hardware orsoftware control logic, ROM, and/or other types of nonvolatile memory.Additional components of the IHS may include one or more disk drives,one or more network ports for communicating with external devices aswell as various I/O devices, such as a keyboard, a mouse, and a videodisplay. The IHS may also include one or more buses operable to transmitcommunications between the various hardware components.

FIG. 1 illustrates a block diagram representation of an example IHS 100,within which one or more of the described features of the variousembodiments of the disclosure may be implemented. Particularly, IHS 100has one or more processor(s) 102 coupled to system memory 130 via systeminterconnect 115. System interconnect 115 may be interchangeablyreferred to as a system bus. System memory 130 may include therein aplurality of software and/or firmware modules including firmware 132,Basic Input/output System (BIOS) 134, Operating System (OS) 136, andapplication(s) 138 (e.g., a licensed virtualization application or thelike). The one or more software and/or firmware modules within systemmemory 130 (e.g., BIOS 134) may be loaded into processor(s) 102 duringoperation of IHS 100.

Processor(s) 102 include several CPU sockets 103, 105, 107, and 109.Each socket includes its respective one or more processing core(s) 104,106, 108, or 110; as well as its associated dedicated memorycontroller(s) and/or I/O lane(s) 112, 114, 116, or 118. In operation,processing cores 104, 106, 108, or 110 may be configured communicatewith each other and with control logic 120. Moreover, control logic 120may control the operation of processing cores 104, 106, 108, or 110.

For example, according to an aspect of the described embodiments,control logic 120 may be configured to control the operating frequencyand voltage or operating state of cores 104, 106, 108, or 110. Controllogic 120 may also receive software and/or firmware modules from systemmemory 130 during the operation of processor(s) 102. In an embodiment,clock 121 is provided on processor(s) 102 and enables the generation ofseveral different periodic frequency signals that may be applied to oneor more of the cores 104, 106, 108, or 110 within one or moreprocessor(s) 102.

IHS 100 also includes one or more input/output (I/O) controllers 140which support connection by, and processing of signals from, one or moreconnected input device(s) 142, such as a keyboard, mouse, touch screen,or microphone. I/O controllers 140 also support connection to andforwarding of output signals to one or more connected output devices144, such as a monitor or display device or audio speaker(s).Additionally, in one or more embodiments, one or more device interfaces146, such as an optical reader, a Universal Serial Bus (USB), a cardreader, Personal Computer Memory Card International Association (PCMCIA)slot, and/or a High-Definition Multimedia Interface (HDMI), may beassociated with IHS 100. Device interface(s) 146 may be utilized toenable data to be read from or stored to corresponding removable storagedevice(s) 148, such as a Compact Disk (CD), Digital Video Disk (DVD),flash drive, or flash memory card. Device interfaces 146 may furtherinclude General Purpose I/O interfaces such as I^(2C), SMBus, andperipheral component interconnect (PCI) buses.

IHS 100 comprises a Network Interface Device (NID) 150. NID 150 enablesIHS 100 to communicate and/or interface with other devices, services,and components that are located external to IHS 100. These devices,services, and components may interface with IHS 100 via an externalnetwork, such as example network 160, using one or more communicationprotocols. Network 160 may be a local area network, wide area network,personal area network, and the like, and the connection to and/orbetween network and IHS 100 may be wired or wireless or a combinationthereof. For purposes of discussion, network 160 is indicated as asingle collective component for simplicity. However, it is appreciatedthat network 160 may comprise one or more direct connections to otherdevices as well as a more complex set of interconnections as may existwithin a wide area network, such as the Internet.

A person of ordinary skill in the art will appreciate that the hardwarecomponents and basic configuration depicted in FIG. 1 and describedherein may vary. For example, the illustrative components within IHS 100are not intended to be exhaustive, but rather are representative tohighlight components that may be utilized to implement systems andmethods described herein. For example, other devices/components may beused in addition to or in place of the hardware depicted. The depictedexample does not convey or imply any architectural or other limitationswith respect to the presently described embodiments and/or the generaldisclosure.

With reference now to FIG. 2, there is illustrated an embodiment of coreconfiguration parameters 210 being transmitted from BIOS 134 to controllogic 120 of processor 102. In the discussion of FIG. 2, reference isalso made to components illustrated in FIG. 1. During the initialstartup of IHS 100 and processor(s) 102, configuration parameters 210are transmitted from the BIOS 134 to processor control logic 120.Configuration parameters 210 may originally have been received from auser, and may include a selection of which of CPU sockets 103, 105, 107,and 109 (or how many) should have their cores enabled withinprocessor(s) 102.

Generally speaking, disabled processing cores do not executeinstructions and do not generate heat, while enabled processing coresexecute instructions at a given frequency that is variable dependingupon processor workloads and other factors that are internal to andbased upon the design of the processor. The foregoing distinctionbetween enabled and disabled processing cores is presented in contrastwith active versus non-active (or idle) cores. When a processing core ismerely idle but nonetheless enabled, it may not be used to executethreads but it still generates heat.

Again, according to some aspects of the disclosure, configurationparameters 210 may identify which (or how many) of processing cores 104,106, 108, or 110 within CPU sockets 103, 105, 107, and 109,respectively, are to be disabled and/or enabled. In some cases,configuration parameters 210 may follow the Advanced Configuration andPower Interface (ACPI) specification. As such, BIOS 134 may loadconfiguration parameters 210 in the form of ACPI Machine Language (AML)bytecode stored in ACPI tables. To make use of these ACPI tables, OS 136may include an interpreter for the AML bytecode.

FIG. 3 is a flowchart illustrating an example of method 300 fortransforming a CPU socket into a memory and/or I/O expander. In thediscussion of FIG. 3, reference is also made to various componentsillustrated in FIGS. 1 and 2. In some embodiments, method 300 may beperformed, at least in part, by BIOS 134 and processor control logic120.

At block 310, one or more of CPU sockets 103, 105, 107, and 109 areinitialized, for example, as part of a BIOS Power-On Self-Test (POST)procedure. At block 320, BIOS 134 may receive user configurationinformation and/or stored profile information. For example, suchinformation may identify a particular core or number of cores to be usedas processing cores; that is, which cores are being enabled asprocessing cores. Additionally or alternatively, the configurationinformation may identify a particular CPU socket or number of CPUsockets to be used as memory and/or I/O expanders; that is, which coreswithin one or more CPU sockets are effectively being disabled asprocessing cores such that they may still be employed as memory and/orI/O bridges for one or more processing cores of other CPU sockets.

At block 330, BIOS 134 may select a CPU socket to be configured. Atblock 340, BIOS 134 determines whether the selected CPU socket is to beconfigured as “FlexMemBridge” or a conventional configuration. In thelatter case, BIOS 134 initializes ACPI tables with conventional ornormal entries at block 350. In the former case, that is, when the CPUsocket is initialized with a FlexMemBridge configuration, the ACPItables are initialized with modified entries at block 360.

At block 370, BIOS 134 determines whether there is another CPU socket tobe configured. If so, control passes to block 330 and the other CPUsocket is selected. Otherwise, control passes to block 380 where the OSis booted.

Referring back to block 360, various embodiments provide for themodification of entries in the ACPI's Local Advanced ProgrammableInterrupt Controller (LAPIC) table, Static Resource Affinity Table(SRAT), System Locality Information Table (SLIT), and/or proximity (PXM)information, for example, as part of configuration parameters 210 ofFIG. 2.

For instance, in a hypothetical scenario, only processing cores 104 and106 may be reported in the LAPIC table, while cores 108 and 110 may beunreported. At block 340, BIOS 134 may create or modify the ACPI's SRATtable, such that memory circuitry 116 may be identified as being coupledto CPU socket 103 (in addition to socket 103's own memory 112), andmemory circuitry 118 may be identified as belonging to CPU socket 105(in addition to socket 105's own memory 114). That is, in a particularsituation where each of memory circuits 112-118 has 12 DIMMs, each ofcores 104 and 106 would effectively have access to 24 DIMMs. The ACPI'sSLIT table may identify memory circuitries 116 and 118 as being remotememories coupled to the CPU sockets 103 and 105, respectively.

In the same hypothetical scenario, ACPI's proximity (PXM) informationmay be modified as part of configuration parameters 210, for instance,to report one or more Peripheral Component Interconnect Express (PCIe)root ports from I/O circuitries 116 and 118 as additional logical PCIeroot ports belonging to CPU sockets 103 and 106, respectively.

Conventional OS and hypervisors use the LAPIC table to detect the numberof sockets in given system. Accordingly, using method 300, from thesoftware's perspective fewer than all of processing cores 104, 106, 108,or 110 within CPU sockets 103, 105, 107, and 109 are present. Moreover,each enabled processing core has at least twice the amount of memoryand/or number of I/O ports; which are borrowed from non-enabled ordisabled cores.

During operation, in response to a System Management Mode (SMM) beinginvoked to address a memory or I/O error of a non-enabled or disabledCPU socket during runtime, the error may be reported having beenoriginated by one of the enabled CPU sockets. For example, still in thesame hypothetical scenario, a memory or I/O error of CPU socket 107(circuitry 116) may be reported as having been originated by CPU socket103, and memory or I/O error of CPU socket 109 (circuitry 118) may bereported as having been originated by CPU socket 105.

Additionally or alternatively, one or more user visible non-OSApplication Programming Interfaces APIs in IHS 100 may be configured toreport a fewer number of processing cores than all available cores,including, for example, BIOS Setup, System Management BIOS (SMBIOS),ACPI, Unified Extensible Firmware Interface (UEFI), Integrated Dell™Remote Access Controller (iDRAC) Graphical User Interface (GUI), and/orthermal/power monitoring interfaces.

FIGS. 4 and 5 illustrate an example of a FlexMemBridge configurationaccording to some embodiments. In this example, processing cores 401 and402 have associated DIMMs 403 and 404, as well as associated I/Ocontrollers 405 and 406, respectively. Ordinarily, as shown in diagram400, core 401 does not have access to circuitries 404 or 406, whereascore 402 does not have access to circuitries 403 or 405. Diagram 500shows the result of application of method 300 to set core 402 inFlexMemBridge configuration. Particularly, core 402 is set into bridgestate such that core 401 has access to DIMMs 404 and I/O 406 viaconnections 501 and 502, respectively, without core 402 being reportedas processing core in the ACPI tables and therefore being unreported tothe OS or other software for licensing purposes. Accordingly, in thisexample, FlexMemBridge configuration 500 provides core 401 without twicethe memory and/or I/O circuitry without increasing licensing costs.

In the above described flowcharts, one or more of the methods may beembodied in a memory device or computer readable medium containingcomputer readable code such that a series of functional processes areperformed when the computer readable code is executed on a computingdevice. In some implementations, certain steps of the methods arecombined, performed simultaneously or in a different order, or perhapsomitted, without deviating from the scope of the disclosure. Thus, whilethe method blocks are described and illustrated in a particularsequence, use of a specific sequence of functional processes representedby the blocks is not meant to imply any limitations on the disclosure.Changes may be made with regards to the sequence of processes withoutdeparting from the scope of the present disclosure. Use of a particularsequence is therefore, not to be taken in a limiting sense, and thescope of the present disclosure is defined only by the appended claims.

Aspects of the present disclosure are described above with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems) and computer program products according to embodiments of thedisclosure. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer program instructions. Computer program code for carrying outoperations for aspects of the present disclosure may be written in anycombination of one or more programming languages, including an objectoriented programming language, without limitation. These computerprogram instructions may be provided to a processor of a general purposecomputer, special purpose computer, such as a service processor, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, performs the method forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks.

As will be further appreciated, the processes in embodiments of thepresent disclosure may be implemented using any combination of software,firmware or hardware. Accordingly, aspects of the present disclosure maytake the form of an entirely hardware embodiment or an embodimentcombining software (including firmware, resident software, micro-code,etc.) and hardware aspects that may all generally be referred to hereinas a “circuit,” “module,” or “system.” Furthermore, aspects of thepresent disclosure may take the form of a computer program productembodied in one or more computer readable storage device(s) havingcomputer readable program code embodied thereon. Any combination of oneor more computer readable storage device(s) may be utilized. Thecomputer readable storage device may be, for example, but not limitedto, an electronic, magnetic, optical, electromagnetic, infrared, orsemiconductor system, apparatus, or device, or any suitable combinationof the foregoing. More specific examples (a non-exhaustive list) of thecomputer readable storage device would include the following: anelectrical connection having one or more wires, a portable computerdiskette, a hard disk, a random access memory (RAM), a read-only memory(ROM), an erasable programmable read-only memory (EPROM or Flashmemory), an optical fiber, a portable compact disc read-only memory(CD-ROM), an optical storage device, a magnetic storage device, or anysuitable combination of the foregoing. In the context of this document,a computer readable storage device may be any tangible medium that cancontain, or store a program for use by or in connection with aninstruction execution system, apparatus, or device.

While the disclosure has been described with reference to exemplaryembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted forelements thereof without departing from the scope of the disclosure. Inaddition, many modifications may be made to adapt a particular system,device or component thereof to the teachings of the disclosure withoutdeparting from the essential scope thereof. Therefore, it is intendedthat the disclosure not be limited to the particular embodimentsdisclosed for carrying out this disclosure, but that the disclosure willinclude all embodiments falling within the scope of the appended claims.Moreover, the use of the terms first, second, etc. do not denote anyorder or importance, but rather the terms first, second, etc. are usedto distinguish one element from another.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The description of the present disclosure has been presented forpurposes of illustration and description, but is not intended to beexhaustive or limited to the disclosure in the form disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope of the disclosure. Thedescribed embodiments were chosen and described in order to best explainthe principles of the disclosure and the practical application, and toenable a person of ordinary skill in the art to understand thedisclosure for various embodiments with various modifications as aresuited to the particular use contemplated.

1. An Information Handling System (IHS), comprising: a plurality ofCentral Processing Unit (CPU) sockets, each of the CPU sockets havingone or more cores, and each of the one or more cores being associatedwith a respective one or more electronic circuits, the one or moreelectronic circuits including at least one of: a memory controller or aninput/output (I/O) controller; and a Basic Input/Output System (BIOS)circuit coupled to the plurality of CPU sockets, the BIOS circuit havingaccess to program instructions that, upon execution by the BIOS, causethe IHS to: initialize the plurality of CPU sockets; and report anelectronic circuit associated to a first core of a first CPU socket asbeing instead associated with a second core of a second CPU socket. 2.The IHS of claim 1, wherein the plurality of CPU sockets include asingle multi-core processor.
 3. The IHS of claim 1, wherein each of corein each of the plurality of CPU sockets is configured to operate as adiscrete logical processor.
 4. The IHS of claim 1, wherein theelectronic circuit associated with the first core of the first CPUsocket is physically disposed closer to the first core than to thesecond core of the second CPU socket.
 5. The IHS of claim 1, whereineach of the memory controllers is configured to communicate with one ormore dual in-line memory modules (DIMMs).
 6. The IHS of claim 1, whereinthe program instructions, upon execution by the BIOS, further cause theIHS to: create or modify a Local Advanced Programmable InterruptController (LAPIC) table of an Advanced Configuration and PowerInterface (ACPI) to: identify at least one of: the second CPU socket ora number of core(s) of the second CPU socket; and not identify the firstCPU socket as having any cores.
 7. The IHS of claim 1, wherein theprogram instructions, upon execution by the BIOS, further cause the IHSto modify an Advanced Configuration and Power Interface (ACPI) StaticResource Affinity Table (SRAT) to identify the memory controllerassociated with the first core of the first CPU socket as being coupleddirectly to the second core of the second CPU socket.
 8. The IHS ofclaim 1, wherein the program instructions, upon execution by the BIOS,further cause the IHS to create or modify an Advanced Configuration andPower Interface (ACPI) System Locality Information Table (SLIT) toidentify the memory controller associated with the first core of thefirst CPU socket as including a remote memory coupled to the second coreof the second CPU socket.
 9. The IHS of claim 1, wherein the programinstructions, upon execution by the BIOS, further cause the IHS tocreate or modify Advanced Configuration and Power Interface (ACPI)proximity (PXM) information to report one or more Peripheral ComponentInterconnect Express (PCIe) root ports associated with the first core ofthe first CPU socket as logical PCIe root ports belonging to the secondcore of the second CPU socket.
 10. The IHS of claim 1, wherein theprogram instructions, upon execution by the BIOS, further cause the IHSto, in response to a System Management Mode (SMM) of operation beinginvoked to address a memory or I/O error of the first core of the firstCPU socket during Operating System (OS) runtime, report the error ashaving been originated by the second core of the second CPU socket. 11.The IHS of claim 1, wherein the reporting operation occurs before theIHS boots into an Operating System (OS).
 12. A computer-implementedmethod, comprising: initializing a plurality of Central Processing Unit(CPU) sockets within a multi-core processor of an Information HandlingSystem (IHS); and prior to the IHS booting an Operating System (OS),reporting an electronic circuit of a first core of a first CPU socket asbelonging to a second core of a second CPU socket.
 13. Thecomputer-implemented method of claim 12, wherein the electronic circuitincludes a memory controller local to the first core of the first CPUsocket.
 14. The computer-implemented method of claim 13, furthercomprising creating or modifying a Local Advanced Programmable InterruptController (LAPIC) table of an Advanced Configuration and PowerInterface (ACPI), wherein the LAPIC table is configured to identify thesecond core of the second CPU socket, and wherein the LAPIC table isconfigured not to identify the first core of the first CPU socket. 15.The computer-implemented method of claim 14, further comprising creatingor modifying an Advanced Configuration and Power Interface (ACPI) StaticResource Affinity Table (SRAT) to identify the memory controller asbeing coupled directly to the second core of the second CPU socket. 16.The computer-implemented method of claim 15, further comprising creatingor modifying an Advanced Configuration and Power Interface (ACPI) SystemLocality Information Table (SLIT) to identify the memory controller asincluding a remote memory coupled to the second core of the second CPUsocket.
 17. The computer-implemented method of claim 11, wherein theelectronic circuit includes an Input/Output (I/O) extender local to thefirst core of the first CPU socket.
 18. The computer-implemented methodof claim 17, further comprising modifying Advanced Configuration andPower Interface (ACPI) proximity (PXM) information to report one or morePeripheral Component Interconnect Express (PCIe) root ports local to thefirst core of the first CPU socket as logical PCIe root ports local tothe second core of the second CPU socket.
 19. The computer-implementedmethod of claim 17, further comprising, in response to a SystemManagement Mode (SMM) of operation being invoked to address a memory orI/O error of the first core of the first CPU socket during OperatingSystem (OS) runtime, reporting the error as having been originated bythe second core of the second CPU socket.
 20. A non-transitorycomputer-readable medium having program instructions stored thereonthat, upon execution by an Information Handling System (IHS), cause theIHS to: initialize a plurality of Central Processing Unit (CPU) sockets;create or modify a Local Advanced Programmable Interrupt Controller(LAPIC) table of an Advanced Configuration and Power Interface (ACPI),wherein the LAPIC table is configured to identify a second core of asecond CPU socket, and wherein the LAPIC table is configured not toidentify a first core of a first CPU socket; create or modify an ACPIStatic Resource Affinity Table (SRAT) to identify a memory controllercorresponding to the first core of the first CPU socket as beingassociated with the second core of the second CPU socket; create ormodify an ACPI System Locality Information Table (SLIT) to identify thememory controller as including a remote memory coupled to the secondcore of the second CPU socket; and in response to a System ManagementMode (SMM) of operation being invoked to address a memory or I/O errorof the first core of the first CPU socket during Operating System (OS)runtime, reporting the error as having been originated by the secondcore of the second CPU socket.